Electrical devices, which may be boards, ICs or embedded cores within ICs, require JTAG interfaces to provide testing and debugging of the device's hardware and software designs. In the past, device test and debug interfaces used the full pin JTAG interface consisting of TDI, TCK, TMS, TRST and TDO signal pins. The TRST pin is optional. More recently, reduced pin JTAG interfaces are being used for test and debug when device pins are not available for the full pin JTAG interface. Substrates, boards or ICs, containing both full and reduced pin JTAG devices will therefore require a full pin JTAG interface for accessing the full pin JTAG devices and a separate reduced pin JTAG interface for accessing the reduce pin JTAG devices. Requiring both a full and reduced pin JTAG interface on substrates complicates test and debug operations. Ideally, and according to the disclosure, substrate test and debug operations should be done without requiring the substrate to have both a full and reduced JTAG interface.
FIG. 1 illustrates an example of a full pin JTAG (FPJ) interface on a device. Full pin JTAG (IEEE 1149.1) interfaces comprising a TDI, TCK, TMS, TRST and TDO signals are well known and broadly used in the industry for testing, debugging, programming and/or other operations.
FIG. 2 illustrates an example of a reduced pin JTAG (RPJ) interface on a device. Reduced pin JTAG interfaces are relatively new in the industry and typically comprised no more than one or two interface signals to carry out test, debug, programming and/or other operations.
FIG. 2A illustrates an addressable type of RPJ interface that requires a clock (CLK) and a data I/O (DIO) signal. This type of RPJ interface is described in detail in a 2006 IEEE International Test Conference paper by Whetsel titled “A High Speed Reduced Pin Count JTAG Interface”, which is incorporated and referenced herein.
FIG. 2B illustrates another addressable type of RPJ interface that requires a clock (TCK) and a data I/O (TMSC) signal. This type of RPJ interface is the subject of developing IEEE standard P1149.7 and described in a 2006 white paper titled “MIPI Test and Debug Interface Framework”, which is incorporated and referenced herein.
FIG. 2C illustrates a non-addressable type of RPJ interface that requires only a single I/O signal referred to as a JTAG Link (JLINK) signal. This JLINK interface was developed by DebugInnovation. The JLINK interface is described on DebugInnovation's website, which is incorporated and referenced herein.
FIG. 2D illustrates a non-addressable type of RPJ interface that requires only a single I/O signal referred to as a Single Wire JTAG (SWJ) signal. This SWJ interface was developed by ARM Ltd. The SWJ interface is described on ARM's website, which is incorporated and referenced herein.
While each of the addressable and non-addressable RPJ interfaces of FIG. 2A-2D are operationally different, they can all be used to achieve a RPJ interface for device test, debug, programming and other operations. Throughout the remainder of this description the term RPJ interface is general and can be used to reference any of the RPJ interfaces shown in FIGS. 2A-2D, as well as any other type of RPJ interface.
FIG. 3 illustrates a substrate 302, which can be a system, board or IC, that includes one or more FPJ (304) devices and one or more RPJ (306) devices. While plural FPJ devices 304 are shown in a daisy-chain, a single FPJ device may exist as well. Further, while plural addressable RPJ devices 306 are shown bussed together, a single non-addressable RPJ device 306 may exist as well. The devices 304-306 can be boards in a system, ICs on a board, or cores within an IC. As seen the FPJ devices 304 require a full pin JTAG interface 308 to a FPJ controller 310 and the RPJ devices 306 require a separate reduced pin interface 312 to a separate RPJ controller 314. Thus for test, debug, programming or other operations, the substrate 302 disadvantageously requires two separate JTAG interface 308 and 312 coupled to two separate JTAG controllers 310 and 314.
The disclosure, as will be described in detail below, does not require substrates 302 to have two separate JTAG interface 308 and 312 each coupled to two separate JTAG controllers 310 and 314. Advantageously therefore, the disclosure provides for substrate test, debug, programming and other operations to FPJ and RPJ devices to occur over a single interface coupled to a single JTAG controller. In the following description JTAG access FPJ or RPJ device interfaces includes access required for device testing, device debug, device programming, or any other operation performed using a FPJ or RPJ device interface.